1. Field of the Invention
The present invention relates to the field of data processing. More particularly, the invention relates to a data processing apparatus having single instruction multiple data (SIMD) processing circuitry.
2. Background
A data processing apparatus may have SIMD processing circuitry for performing a SIMD operation on first and second operands comprising multiple data elements. The SIMD processing circuitry has several parallel lanes of processing which each perform a particular operation on corresponding data elements of the first and second operands. For example, the first and second operands may each comprise 32-bit data values, with each operand including four 8-bit data elements. A SIMD addition operation may perform four 8-bit additions in parallel on each pair of 8-bit data elements.
Sometimes, the order in which the data elements appear within the operands may not be the same as the order in which the data elements are to be combined by the SIMD operation, and so it may be necessary to perform some rearrangement of data elements prior to performing the SIMD operation. The present technique seeks to improve the implementation of such rearrangements to improve the performance of SIMD processing operations.